The India–EU Summit’s 2030 Agenda reflects strong strategic intent in semiconductor cooperation, but its structural gaps remain unaddressed
The 16th India-EU Summit, held on 27 January, produced the ’Towards 2030 Comprehensive Strategic Agenda’, which outlined the semiconductor provisions through joint R&D on chip design, heterogeneous integration, reciprocal talent exchanges, and a dedicated framework for AI chip applications. On paper, it is the most substantive institutional commitment the two partners have produced on technology cooperation.
But there is a clear difference between ambition and implementation. Despite the strategic intent of the semiconductor commitments that the Agenda has made, its structural gaps remain unaddressed: the lack of a coordinating mechanism between the EU Chips Act and Semiconductor Mission in India; the lack of a talent exchange model with an effective pathway to industrial repatriation; and the lack of a coordinating OSAT agenda that has achieved no demand side anchor. Compared to the history of the US-India iCET, which turned dialogue into investment, the India-EU partnership casts doubt on institutional structure rather than political will.
A closer look at the Agenda shows a familiar pattern. Its semiconductor provisions are significantly similar to those made at the 2022 and 2023 Trade and Technology Council (TTC) ministerial meetings. A few of the previous agreements have not incorporated specific performance goals, designated institutional heads or accountability procedures. Despite its lofty goals, the 2026 Agenda makes little difference. It brings layers of language to an infrastructure that has not yet generated a commercial anchor for investment.
The comparison with the US-India iCET is something worth taking a close look at. Launched in 2023, iCET helped Micron’s US$825 million Assembly, Testing, Marking, and Packaging (ATMP) investment to be cleared in Gujarat in less than 18 months. That pace was possible because iCET worked through a direct channel between the national security councils of both governments and so had the authority to coordinate federal incentives and to cut through administrative timelines in ways that a trade diplomacy forum cannot.
The Towards 2030 Agenda, similar to its predecessors, has bold objectives but has yet to establish the mechanisms required to implement them.
The India-EU TTC operates very differently. It does not have any comparable institutional channel, no anchor investment in place currently, and no agreed mechanism to coordinate the EU Chips Act and India's Semiconductor Mission as complementary programmes. The two initiatives have broadly similar goals, but have evolved independently, and there has not been a joint funding vehicle or a common delivery framework to align them. Until then, the TTC will continue to function as an arena for building consensus more than as a mechanism for driving investment.
The EU Chips Act and India's Semiconductor Mission were designed separately and continue to function in that manner. STMicroelectronics, Infineon and NXP are companies with some direct commercial exposure to India's burgeoning automotive and industrial chip market but no presence in India's fabrication (fab) ecosystem. A bilateral Technology Investment Corridor with co-financing provided from both programmes, modelled on EU-US Chips Act coordination frameworks, would be a good starting point for closing this gap.
India has a semiconductor design workforce that accounts for about 20 percent of the global design workforce and is routinely mentioned as the most interesting asset of the partnership. Yet the provisions of the Towards 2030 Agenda on talent exchange help in channelling Indian engineers to European-based research institutions like the Interuniversity Microelectronics Centre (imec), Fraunhofer and French Alternative Energies and Atomic Energy Commission (CEA-Leti) without a proper pipeline back for that expertise to Indian industry. The result is that the partnership, as presently designed, risks increasing brain drain as opposed to building domestic capacity. Conditioning talent exchanges on intellectual property (IP) co-location, where any process design kit (PDK) co-developed by an Indian researcher at a European institution has a licensing provision with Indian foundries, would make the programme consistent with its stated supply chain objectives.
India's OSAT and ATMP opportunity is well-documented, and the 2030 Agenda identifies this as one of the priority areas for cooperation. What it lacks is a commitment on the demand side to make that opportunity commercially viable. No EU automotive Original Equipment Manufacturer (OEM) or Tier-1 supplier has agreed to procure back-end services from India, and no procurement framework has been proposed under the TTC. The Micron investment worked because there was a named anchor- federal incentives and land allocation at the state level at the same time. Three years on, into the Trade and Technology Council (TTC), no equivalent convergence has been attempted with a European partner.
The most direct means to move the Semiconductor Memorandum of Understanding (MoU) from a statement of intent to a delivery mechanism is to attach it to a specific commercial commitment. The CG Power-Renesas joint venture in Sanand, Gujarat, provides an applicable model. Japan's Renesas Electronics anchored a US$870 million chip packaging facility by aggregating ISM central incentives equalling 50 percent of project costs, Gujarat state government land allocation, and a defined procurement commitment from Renesas's own global automotive supply chain. Crucially, the deal was closed because a named foreign anchor firm concurrently brought capital and guaranteed demand. STMicroelectronics and Infineon, both of which have large shares of the global automotive semiconductor market and have established design operations in Bengaluru, Hyderabad, and Noida, are natural EU equivalents to this approach. Converting the MoU to a time-bound Investment Triggering Agreement, with co-financing from both the EU Chips Act, ISM, and a named anchor firm committed to a facility or procurement arrangement within 18 months, would be a replication of the Renesas model with a European partner.
The solution is not to cut down on talent exchanges but to modify the terms on which they operate. Currently, there is nothing in the Semiconductor MoU nor in the 2030 Agenda that prevents intellectual property (IP) created as a result of jointly funded research from being registered exclusively in the European jurisdiction. Requiring any process design kit (PDK) or design methodology co-developed by an Indian researcher at a European institution to be jointly registered with a licensing provision for Indian foundries would bring the commercial value of such exchanges back into India's industrial base. This is not a novel model: the US-India iCET framework has followed similar joint ownership principles when it comes to defence technology co-production. It is only necessary to extend the same logic to civilian semiconductor research under TTC, with a targeted amendment to the existing IP provisions in the MoU.
India has set a goal of a 10 percent share in the global OSAT and ATMP market in five years, and European car suppliers, who export close to 10 billion euros worth of components to India, have a direct commercial stake in that goal. The template for the way that demand-side commitment can trigger this opportunity already exists. In July 2025, Tata Electronics and Germany's Robert Bosch GmbH signed an MoU for chip packaging and manufacturing collaboration across Tata's ATMP facility in Assam and foundry in Gujarat, with Bosch explicitly citing supply chain resilience for automotive electronics as the reason for entering the collaboration. That bilateral corporate agreement has advanced more rapidly than anything generated under the Trade and Technology Council (TTC). Formalising a similar procurement commitment from at least one EU automotive Original Equipment Manufacturer (OEM) consortium in the context of the TTC, with an agreed sourcing volume by 2028, would transform a private precedent into a structural anchor.
The India-EU semiconductor alliance is not short on ambition. Where it has scope to improve is in building the institutional machinery to convert that ambition into investment. The Towards 2030 Agenda, similar to its predecessors, has bold objectives but has yet to establish the mechanisms required to implement them. Closing that gap does not demand a new framework. It requires making the existing framework more accountable. A named anchor investment, IP terms that will restore value to the Indian industry, and a procurement commitment that can make the Indian OSAT opportunity feasible to European partners are all steps that can be taken. They are the bare minimum requirements of a partnership that has spent three years in dialogue and must now deliver results.
Veer Puri is a Research Assistant with ORF’s Centre for New Economic Diplomacy.
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Veer Puri is a Research Assistant with ORF’s Centre for New Economic Diplomacy. At ORF, his research focuses on the Blue Economy and connectivity, with particular ...
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